It is well known in the field of integrated circuit (IC) design and manufacture to provide protection to IC packages against electro-static discharge (ESD) events. ESD events are occurrences of short, fast and high amplitude electrical current pulses caused by the transfer of electrical charge between two bodies of different potential.
For analogue applications, and in particular for analogue applications requiring a high standard of reliability, ESD protection circuitry is required to provide protection against significant ESD. Examples of such applications include, by way of example, automotive systems, such as anti-lock brake systems (ABS), airbag deployment systems, electronic stabilisation program (ESP) systems, etc.
For such applications requiring a high standard of reliability, it is known for circuitry to be subjected to ESD gun testing, such as that defined in International Electrotechnical Commission (IEC) 61000-4-2, as published on 30 May 2005, and International Standards Organisation (ISO) standard ISO 10605 as published on 7 Jul. 2008. In such testing, an ESD pulse is generated by a ‘gun’, and applied to the pins of an IC under test. The ESD gun may be charged up to 25 kVolts prior to being discharged through a resistor of 330 Ohms or 2 Kohms, depending upon the specification. Thus, the current peak can reach 90 Amps.
In the field of automotive electronics, the so-called Local Interconnect Network (LIN) bus is a vehicle bus standard specified by the LIN consortium. In relation to devices intended to operate on a LIN bus, the standards identified above and the LIN conformance specification together require a pin that is to be coupled to the LIN bus to withstand the gun test at +8 kV and −8 kV for a peak current close to 30.
In order to protect an integrated circuit from ESD events, a so-called Silicon-Controlled Rectifier (SCR) circuit is known to provide adequate protection against such ESD events for many applications. In this respect, an SCR circuit has so-called “snapback” characteristics and so has an associated current-voltage characteristic that is S-shaped in a forward direction. The SCR is therefore able to provide an open circuit between a first terminal and a second terminal when a voltage applied across the first and second terminals is positive, but less than a predetermined trigger voltage. The first terminal is coupled to a node in the integrated circuit that is to be protected, and the second terminal is typically coupled to ground potential.
However, when the voltage applied across the first and second terminals matches or exceeds the trigger voltage, a low resistance current path is provided between the first and second terminals and is maintained until the voltage applied across the first and second terminals falls below a predetermined holding or snapback voltage. The snapback voltage is less than the trigger voltage. The SCR circuit described above is not bidirectional and can only handle ESD events that have a positive polarity.
U.S. Pat. No. 6,784,029 describes a structure that provides an SCR that supports bi-directional triggering and an adjustable trigger voltage. In this respect, an n-type epitaxial layer is formed on a p-type substrate. A first p-region and a second p-region are formed in the n-type epitaxial layer and a first p+ region is formed in the first p-region and a first n+ region is formed in the first p-region, the first p+ region and the first n+ region being laterally spaced with respect to each other. Similarly, a second p+ region is formed in the second p-region and a second n+ region is formed in the second p-region, the second p+ region and the second n+ region being laterally spaced with respect to each other. The first p+ region and the first n+ region are coupled to a first common contact and the second p+ region and the second n+ region are coupled to a second common contact. During operation, the first p-region, the n-type epitaxial layer and the second p-region of the structure provide a PNP transistor. Similarly, the second n+ region, the second p-region and the n-type epitaxial region of the structure provide an NPN transistor to which the PNP transistor is coupled to form a thyristor circuit.
Whilst the above thyristor circuit has an adjustable trigger voltage by using the PNP transistor having a “floating” base terminal (the base-emitter junction has a very high impedance), a very low capacitive current is allowed to make the base-emitter junction of the PNP transistor forward biased. Consequently, an electric current of an ElectroMagnetic Interference (EMI) event causes the PNP transistor to switch to an on-state and drive current during the EMI event. Also, the SCR circuit of U.S. Pat. No. 6,784,029 is triggered by virtue of triggering of the NPN transistor.